Quarter-rate speculative decision feedback equalizer

ABSTRACT

According to an aspect of an embodiment of the present disclosure, a method of relaxing a timing constraint associated with reducing inter-symbol interference (ISI) of input data includes adding an ISI cancellation value to input data received at a first clock rate to generate first speculative data. The method further includes subtracting the ISI cancellation value from the input data to generate second speculative data. The method also includes sampling the first speculative data and the second speculative data at a second clock rate that is one-fourth of the first clock rate such that a timing constraint associated with performing the ISI reduction is relaxed.

FIELD

The embodiments discussed herein are related to decision feedback equalizers (DFE).

BACKGROUND

Many electronic systems have complex architectures that include many integrated circuits (IC's) that communicate with each other at increasingly higher data signal speeds. However, the higher speeds of data signals communicated between IC's may lead to signal degeneration in the form of pulse dispersion and inter-symbol interference (ISI) that may degrade the signal-to-noise ratio (SNR) of the data signals. One common way to compensate for such degeneration is to implement a decision feedback equalizer (DFE) circuit. However, conventionally configured DFE circuits may not operate at speeds fast enough for compensating for signal degeneration of high-speed data signals.

The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one example technology area where some embodiments described herein may be practiced.

SUMMARY

According to an aspect of an embodiment, a method of relaxing a timing constraint associated with reducing inter-symbol interference (ISI) of input data includes adding an ISI cancellation value to input data received at a first clock rate to generate first speculative data. The method further includes subtracting the ISI cancellation value from the input data to generate second speculative data. The method also includes sampling the first speculative data and the second speculative data at a second clock rate that is one-fourth of the first clock rate such that a timing constraint associated with performing the ISI reduction is relaxed.

The object and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

FIG. 1 illustrates a block diagram of an example decision feedback equalizer (DFE) circuit;

FIG. 2A illustrates an example of a single-tap speculative DFE circuit configured to operate at a quarter-clock rate;

FIG. 2B illustrates timing associated with the single-tap speculative DFE circuit of FIG. 2A;

FIGS. 3A and 3B illustrate an example of a dual-tap speculative DFE circuit configured to operate at a quarter-clock rate; and

FIG. 4 is a flow chart of an example method of relaxing a timing constraint associated with reducing inter-symbol interference (ISI) of input data.

DESCRIPTION OF EMBODIMENTS

As described in further detail below, a speculative decision feedback equalizer (DFE) circuit may be configured in a manner such that inter-symbol interference (ISI) experienced by data received by the speculative DFE circuit may be performed at a clock rate that is one-fourth of the clock rate of the input data. Therefore, the timing constraints imposed on the speculative DFE circuit may be relaxed, which may allow for higher clock rates of the received input data.

Embodiments of the present invention will be explained with reference to the accompanying drawings.

FIG. 1 illustrates a block diagram of an example DFE circuit 100. The DFE circuit 100 may be configured to receive input data 101 from a circuit of an electronic system over a communication channel or from some other source. The input data 101 may experience inter-symbol interference (ISI) when different bits of the input data 101 interfere with each other during propagation over the communication channel. The ISI may make it difficult or impossible to read the input data 101. Therefore, the DFE circuit 100 may be configured to compensate for at least some of the ISI experienced by the input data 101 such that the input data 101 may be more easily read.

The DFE circuit 100 may compensate for ISI by applying ISI cancellation values to the input data 101 that may be based on one or more previous values (e.g., bit value) of the input data 101. The number of previous values of the input data 101 used to compensate for ISI may be associated with a number of taps 106 of the DFE circuit 100. For example, a one-tap DFE circuit 100 may compensate for ISI based on a first preceding value of the input data 101, a two-tap DFE circuit 100 may compensate for ISI based on first and second preceding values of the input data 101, etc. Accordingly, application of the ISI cancellation values to the input data 101 may result in output data 108 that may have at least a portion of the ISI cancelled therefrom.

Each of the taps 106 of the DFE circuit 100 may be configured to receive an associated previous value of the input data 101 and may apply an associated ISI cancellation value to the input data 101 based on the associated previous value. For example, the DFE circuit 100 may include a flip-flop 104 a configured such that the output of the flip-flop 104 a is the previous value of the input data 101. A tap 106 a may be configured to receive the previous value and, based on the previous value (e.g., whether the previous value was a “1” or a “0”), the tap 106 a may add a cancellation value C₁ to the input data 101 or subtract the cancellation value C₁ from the input data 101 via a summer 102. Accordingly, the tap 106 a may compensate for ISI experienced by the input data 101 that may be caused by a previous value of the input data 101. In some embodiments, the DFE circuit 100 may include any number of additional taps 106 b-106 n and flip-flops 104 b-104 n similarly configured to compensate for ISI experienced by the input data 101 that may be caused by the second through nth previous values of the input data 101. Modifications, additions, or omissions may be made to the DFE circuit 100 without departing from the scope of the present disclosure. For example, the DFE circuit 100 may be configured to have any number of taps 106 depending on the desired application and implementation of the DFE circuit 100.

As the data rate of the input data received by a DFE circuit increases, timing constraints imposed on the DFE circuit for compensating for ISI may be tighter. Therefore, a DFE circuit may be configured as a speculative DFE circuit to improve the timing constraints imposed on the DFE circuit. A speculative DFE circuit may add an ISI cancellation value, such as the cancellation value C₁, to input data to generate first speculative data associated with the addition of the ISI cancellation value. The speculative DFE circuit may also subtract the ISI cancellation value from the input data at the same time the addition is occurring to generate second speculative data associated with the subtraction of the ISI cancellation value. The speculative DFE circuit may use a digital filter to select which of the first or second speculative data to use as output data based on one or more previous values of the input data. Accordingly, the speed of a speculative DFE circuit may be increased as compared to a non-speculative DFE circuit because the addition or subtraction associated with an ISI cancellation value may be performed before having to determine a previous value of input data.

As mentioned above and detailed below, a speculative DFE circuit implemented according to the present disclosure may be configured such that the speculative ISI cancellation may be performed at a clock rate that is one-fourth of the data rate of input data. As detailed below with respect to FIGS. 2A, 2B, and 3, such an implementation may be accomplished through demultiplexing speculative data associated with the input data such that values of the input data may have ISI compensation performed thereon in a parallel manner. Therefore, through a speculative quarter-rate implementation, the timing constraints imposed on the speculative DFE circuit may be relaxed to allow for faster data rates of the input data.

FIG. 2A illustrates an example single-tap speculative DFE circuit 200 (hereinafter “DFE Circuit 200”) configured to operate at a quarter-clock rate, arranged in accordance with at least some embodiments of the present disclosure. The DFE circuit 200 may include a speculative analog circuit 202 configured to receive input data 201. The input data 201 may include a plurality of values 209 (depicted in FIG. 2B) that may include one or more bits of information. The DFE circuit 200 may receive the values 209 of the input data 201 in a sequential manner based on a clock 203 (depicted in FIG. 2B as Clk).

The speculative analog circuit 202 may include summing circuits 212 a, 212 b, 214 a, and 214 b that may each receive the input data 201. The summing circuits 212 a and 214 a may be configured to add an ISI cancellation value C₁ to the received input data 201 to generate speculative data 211 a and 213 a, respectively. The summing circuits 212 b and 214 b may be configured to add a negative of the ISI cancellation value C₁ to the input data 201 to thus subtract the ISI cancellation value C₁ to generate speculative data 211 b and 213 b, respectively. The ISI cancellation value C₁ may be associated with cancelling ISI experienced by a value 209 of the input data 201 from the previous value 209 of the input data 201. The summing circuits 212 a and 212 b and 214 a and 214 b may be communicatively coupled to a half-rate sampling circuit 204.

The half-rate sampling circuit 204 may include flip-flops 216 a and 216 b, communicatively coupled to the summing circuits 212 a and 212 b, respectively. Therefore, the flip-flop 216 a receives the speculative data 211 a from the summing circuit 212 a and the flip-flop 216 b receives the speculative data 211 b from the summing circuit 212 b. Similarly, the half-rate sampling circuit 204 may include flip-flops 218 a and 218 b communicatively coupled to the summing circuits 214 a and 214 b, respectively. Accordingly, the flip-flop 218 a receives the speculative data 213 a from the summing circuit 214 a and the flip-flop 218 b receives the speculative data 213 b from the summing circuit 214 b.

The flip-flops 216 a and 216 b of the half-rate sampling circuit 204 may be configured to sample the speculative data 211 a and 211 b on a rising edge of a half-clock 205 (depicted in FIG. 2B as Hclk). The rising edge of the half-clock 205 is illustrated as Hclk, in FIG. 2A. The flip-flops 218 a and 218 b of the half-rate sampling circuit 204 may be configured to sample the speculative data 213 a and 213 b on a falling edge of the half-clock 205. The falling edge of the half-clock 205 is illustrated as Hclk_(f) in FIG. 2A.

As the name denotes, and as illustrated in FIG. 2B, the half-clock 205 may have a rate that is one-half of the rate of the clock 203. Therefore, the flip-flops 216 a and 216 b may sample the speculative data 211 a and 211 b, respectively, associated with every other value 209 of the input data 201. Additionally, the flip-flops 218 a and 218 b may sample the speculative data 213 a and 213 b, respectively, associated with the other values 209 of the input data 201.

For example, as illustrated in FIG. 2B, at a time t₁ the input data 201 may have a value 209 e. Accordingly, at the time t₁, the speculative data 211 a, 211 b, 213 a, and 213 b may be associated with the value 209 e. Additionally, at the time t₁, the half-clock 205 may go from “low” to “high” such that the rising edge of the half-clock 205 occurs at the time t₁. Therefore, at the time t₁, the flip-flops 216 a and 216 b may sample the speculative data 211 a and 211 b, respectively, such that the speculative data 211 a and 211 b sampled by the flip-flops 216 a and 216 b at the time t₁ may be associated with the value 209 e of the input data 201. However, the flip-flops 218 a and 218 b may not sample the speculative data 213 a and 213 b, respectively, at the time t₁ because the flip-flops 218 a and 218 b may be configured to sample on the falling edge of the half-clock 205, not the rising edge.

At a time t₂, the half-clock 205 may go from “high” to “low” such that the falling edge of the half-clock 205 may occur at the time t₂. Therefore, the flip-flops 218 a and 218 b may sample the speculative data 213 a and 213 b, respectively, at the time t₂. Further, as illustrated in FIG. 2B, the input data 201 may have a value 209 f at the time t₂ such that the speculative data 213 a and 213 b sampled by the flip-flops 218 a and 218 b, respectively, at the time t₂ may be associated with the value 209 f of the input data 201. Additionally, at the time t₂, the flip-flops 216 a and 216 b may not sample the speculative data 211 a and 211 b, respectively, because the flip-flops 216 a and 216 b may be configured to sample on the rising edge of the half-clock 205, not the falling edge.

Therefore, the outputs of the flip-flops 216 a and 216 b, may be “even” speculative data 215 a and 215 b, respectively, that may be associated with an “even” value 209 (e.g., the value 209 e) of the input data 201. Further, the outputs of the flip-flops 218 a and 218 b may be “odd” speculative data 217 a and 217 b, respectively, that may be associated with an “odd” value 209 of the input data 201. The terms “even” and “odd” are used to denote that “even” values 209 of the input data 201 are sequentially next to “odd” values 209 of the input data 201 in the same manner that “even” integers may be sequentially next to “odd” integers in an integer sequence incremented by one. The terms “even” and “odd” do not denote or correspond to the actual information (e.g., a “1” bit or a “0” bit) included in the values 209. Accordingly, the half-rate sampling circuit 204 may demultiplex speculative data 211 a and 211 b, and 213 a and 213 b associated with consecutive values 209 of the input data 201 (e.g. values 209 e and 209 f) into parallel outputs of even speculative data 215 a and 215 b and odd speculative data 217 a and 217 b.

The flip-flops 216 a and 216 b may be communicatively coupled to flip-flops 220 a and 220 b, respectively, of a half-rate aligning circuit 206 such that the flip-flops 220 a and 220 b receive the even speculative data 215 a and 215 b from the flip-flops 216 a and 216 b, respectively. The flip-flops 218 a and 218 b may be communicatively coupled to flip-flops 220 c and 220 d, respectively, of the half-rate aligning circuit 206 such that the flip-flops 220 c and 220 d receive the odd speculative data 217 a and 217 b from the flip-flops 218 a and 218 b, respectively.

The flip-flops 220 a-220 d may be configured to sample the even speculative data 215 a and 215 b and the odd speculative data 217 a and 217 b, on the rising edge of the half-clock 205 such that the even speculative data 215 a and 215 b may be substantially time aligned with the odd speculative data 217 a and 217 b at the outputs of the flip-flops 220 a-220 d. The outputs of the flip-flops 220 a-220 d may be outputs of the half-rate aligning circuit 206.

The half-rate aligning circuit 206 may be communicatively coupled to a quarter-rate sampling circuit 208 configured to sample the even speculative data 215 a and 215 b, and the odd speculative data 217 a and 217 b based on a quarter-clock 207 (depicted in FIG. 2B as (Qclk). A rising edge of the quarter-clock 207 is illustrated as Qclk_(r) in FIG. 2A. A falling edge of the quarter-clock 207 is illustrated as Qclk_(f) in FIG. 2A. The quarter-clock 207 may be configured at a rate that is one-fourth of the rate of the clock 203, as illustrated in FIG. 2B.

The quarter-rate sampling circuit 208 may include flip-flops 222 a-222 d and 224 a-224 d arranged in sets where each set may be configured to receive one of the even speculative data 215 a or 215 b, or the odd speculative data 217 a or 217 b from a respective flip-flop of the flip-flops 220 a-220 d. For example, the flip-flops 222 a and 224 a may be a set of flip-flops configured to receive the even speculative data 215 a from the flip-flop 220 a, the flip-flops 222 b and 224 b may be a set of flip-flops configured to receive the even speculative data 215 b from the flip-flop 220 b, the flip-flops 222 c and 224 c may be a set of flip-flops configured to receive the odd speculative data 217 a from the flip-flop 220 c, and the flip-flops 222 d and 224 d may be a set of flip-flops configured to receive the odd speculative data 217 b from the flip-flop 220 d.

The flip-flops 222 a-222 d may be configured to sample the even speculative data 215 a or 215 b, or the odd speculative data 217 a or 217 b respectively received by each of the flip-flops 222 a-222 d on the rising edge of the quarter-clock 207. The flip-flops 224 a-224 d may be configured to sample the even speculative data 215 a or 215 b, or the odd speculative data 217 a, or 217 b respectively received by each of the flip-flops 224 a-224 d on the falling edge of the quarter-clock 207.

The quarter-rate sampling circuit 208 may demultiplex even speculative data 215 a and 215 b associated with consecutive even values 209 of the input data 201 into parallel outputs of even speculative data 219 a and 219 b and next-even speculative data 223 a and 223 b. For example, the even speculative data 219 a and 219 b may be associated with the even value 209 e of the input data 201 and the next-even speculative data 223 a and 223 b may be associated with the next even value 209 g of the input data 201.

The quarter-rate sampling circuit 208 may also demultiplex odd speculative data 217 a and 217 b associated with consecutive odd values 209 of the input data 201 into parallel outputs of odd speculative data 221 a and 221 b and next-odd speculative data 225 a and 225 b. For example, the odd speculative data 221 a and 221 b may be associated with the odd value 209 f of the input data 201 and the next-odd speculative data 225 a and 225 b may be associated with the odd value 209 h of the input data 201.

Consider an example of data flow through quarter-rate sampling circuit 208 in which the even speculative data 215 a sampled by the flip-flop 222 a on the rising edge of the quarter-clock 207 may be associated with an “even” value 209 e of the input data 201. Therefore, the even speculative data 219 a output by the flip-flop 222 a may be associated with the “even” value 209 e of the input data 201. Additionally, due to the quarter rate of the quarter clock 207, the even speculative data 215 a sampled by the flip-flop 224 a on the next falling edge of the quarter-clock 207 may be associated with the “even” value 209 g of the input data 201, which may be the next even value 209 after the even value 209 e. Therefore, the next-even speculative data 223 a output by the flip-flop 224 a may be associated with the next even value 209 with respect to the even value 209 associated with the even speculative data 219 a. As such, the flip-flops 222 a and 224 a may demultiplex the even speculative data 215 a into parallel outputs of even speculative data 219 a and next-even speculative data 223 a that may be associated with consecutive even values 209 of the input data 201. The flip-flops 222 b, 222 c, and 222 d and 224 b, 224 c, and 224 d may similarly demultiplex the even speculative data 215 b, the odd speculative data 217 a, and the odd speculative data 217 b, respectively, into parallel outputs of even speculative data 219 b and next-even speculative data 223 b, odd speculative data 221 a and next-odd speculative data 225 a, and odd speculative data 221 b and next-odd speculative data 225 b, respectively.

A quarter-rate aligning circuit 210 of the DFE circuit 200 may include flip-flops 226 a-226 h each configured to receive one of the even speculative data 219 a and 219 b, the odd speculative data 221 a and 221 b, the next-even speculative data 223 a and 223 b, and the next-odd speculative data 225 a and 225 b. The flip-flops 226 a-226 h of the quarter-rate aligning circuit 210 may be configured to sample the respective speculative data on the rising edge of the quarter-clock 207. Therefore, the even speculative data 219 a and 219 b, the odd speculative data 221 a and 221 b, the next-even speculative data 223 a and 223 b, and the next-odd speculative data 225 a and 225 b may be substantially time aligned at the outputs of the flip-flops 226. The outputs of the flip-flops 226 may be the outputs of the quarter-rate aligning circuit 210. The time aligned even speculative data 219 a and 219 b, odd speculative data 221 a and 221 b, next-even speculative data 223 a and 223 b, and next-odd speculative data 225 a and 225 b may be received from the quarter-rate aligning circuit 210 by a digital filter 231.

The digital filter 231 may include a selector 228 a configured to receive the even speculative data 219 a and 219 b from the flip-flops 226 a and 226 b of the quarter-rate aligning circuit 210. The selector 228 a may be configured to select one of the even speculative data 219 a or 219 b to generate output data 227 a. The output data 227 a may accordingly be associated with a value 209 of the input data 201 that may be associated with the even speculative data 219 a and 219 b. For example, the even speculative data 219 a and 219 b may be associated with a value 209 e such that the output data 227 a may be associated with the value 209 e.

The digital filter 231 may include a selector 228 b configured to receive the odd speculative data 221 a and 221 b from the flip-flops 226 c and 226 d of the quarter-rate aligning circuit. The selector 228 b may be configured to select one of the odd speculative data 221 a or 221 b to generate output data 227 b associated with a value 209 of the input data 201 that may be associated with the odd speculative data 221 a and 221 b. The value 209 associated with the output data 227 b may be the next value 209 with respect to the value 209 associated with the output data 227 a. For example, the value 209 associated with the output data 227 b may be the value 209 f when the value 209 associated with the output data 227 a is the value 209 e.

The digital filter 231 may include a selector 228 c configured to receive the next-even speculative data 223 a or 223 b from the flip-flops 226 e and 226 f of the quarter-rate aligning circuit. The selector 228 c may be configured to select one of the next-even speculative data 223 a and 223 b to generate an output data 227 c associated with a value 209 of the input data 201 that may be associated with the next-even speculative data 223 a and 223 b. The value 209 associated with the output data 227 c may be the next value 209 with respect to the value 209 associated with the output data 227 b. For example, the value 209 associated with the output data 227 c may be the value 209 g when the value 209 associated with the output data 227 b is the value 209 f.

The digital filter 231 may include a selector 228 d configured to receive the next-odd speculative data 225 a and 225 b from the flip-flops 226 g and 226 h of the quarter-rate aligning circuit. The selector 228 d may be configured to select one of the next-odd speculative data 225 a or 225 b to generate output data 227 d associated with a value 209 of the input data 201 that may be associated with the next-odd speculative data 225 a and 225 b. The value 209 associated with the output data 227 d may be the next value 209 with respect to the value 209 associated with the output data 227 c. For example, the value 209 associated with the output data 227 d may be the value 209 h when the value 209 associated with the output data 227 c is the value 209 g.

The output data 227 a-227 d may be received by flip-flops 230 a-230 d, respectively. The flip-flops 230 a-230 d may be configured to output previous-output data 229 a-229 d until sampling the respectively received output data 227 on the rising edge of the quarter-clock 207.

The value 209 associated with the previous-output data 229 output by a flip-flop 230 may be the fourth previous value 209 associated with the output data 227 received at the input of the flip-flop 230 because the clock rate of the quarter-clock 207 may be one fourth of the clock rate of the clock 203. For example, the previous-output data 229 a output by the flip-flop 230 a may be associated with a value 209 a of the input data 201 if the output data 227 a received at the input of the flip-flop 230 a is associated with a value 209 e of the input data 201; the previous-output data 229 b output by the flip-flop 230 b may be associated with a value 209 b of the input data 201 if the output data 227 b received at the input of the flip-flop 230 b is associated with a value 209 f of the input data 201; the previous-output data 229 c output by the flip-flop 230 c may be associated with a value 209 c of the input data 201 if the output data 227 c received at the input of the flip-flop 230 c is associated with a value 209 g of the input data 201; and the previous-output data 229 d output by the flip-flop 230 d may be associated with a value 209 d of the input data 201 if the output data 227 d received at the input of the flip-flop 230 d is associated with a value 209 h of the input data 201.

The selectors 228 a-228 d may be configured to select one of the respectively received speculative data based on the output data associated with the value 209 that may be previous to the value 209 associated with the received speculative data. For example, the previous-output data 229 d may be associated with a value 209 of the input data 201 (e.g., the value 209 d) that may be previous to the value 209 of the input data 201 associated with the even speculative data 219 a and 219 b received by the selector 228 a (e.g. the value 209 e).

Accordingly, the selector 228 a may select the even speculative data 219 a or 219 b based on the previous-output data 229 d. The selector 228 b may similarly select one of the odd speculative data 221 a or 221 b based on the output data 227 a because, as described above, the output data 227 a may be associated with a value 209 of the input data 201 that may be previous to the value 209 of the input data 201 associated with the odd speculative data 221 a and 221 b. The selector 228 c may similarly select one of the next-even speculative data 223 a or 223 b based on the output data 227 b because, as described above, the output data 227 b may be associated with a value 209 of the input data 201 that may be previous to the value 209 of the input data 201 associated with the next-even speculative data 223 a and 223 b. Further, the selector 228 d may similarly select one of the next-odd speculative data 225 a or 225 b based on the output data 227 c because, as described above, the output data 227 c may be associated with a value 209 of the input data 201 that may be previous to the value 209 of the input data 201 associated with the next-odd speculative data 225 a and 225 b.

Therefore, the digital filter 231 may be configured to generate output data 227 a-227 d associated with four consecutive values 209 of the input data 201 in a parallel manner. This parallel configuration caused by sampling at one-fourth the clock rate of the clock 203 may relax a timing constraint associated with the operations of the digital filter because the output data 227 a-227 d may be sampled by the flip-flops 230 a-230 d at a clock rate that is one-fourth of the clock rate associated with the input data 201. Therefore, the time constraints imposed on the digital filter 231 may be relaxed.

For example, the timing constraint of the DFE 200 of FIG. 2 may be based on a critical path associated with the digital filter 231, where the following operations may need to be performed by the digital filter 231 between rising edges of the quarter-clock 207: (1) the flip-flop 230 d may output previous-output data 229 d; (2) the selector 228 a may make a selection for the output data 227 a based on the recently outputted previous-output data 229 d; (3) the selector 228 b may make a selection for the output data 227 b based on the recently selected output data 227 a; (4) the selector 228 c may make a selection for the output data 227 c based on the recently selected output data 227 b; and (5) the selector 228 d may make a selection for the output data 227 d based on the recently selected output data 227 c. The timing requirements associated with such a critical path may be expressed by the following equation:

4UI<t _(cq,FF) +t _(setup,FF)+4*t _(sq,MUX)

“UI” of the above equation may represent a “Unit Interval” that may be associated with a time period between values 209 of the input data 201 and “4UI” may be associated with the timing constraint of the DFE circuit 200. Additionally, in the above equation, “t_(cq,FF)” may represent the delay of the flip-flop 230 d from the time of receiving the rising edge of the quarter-clock signal 207 to outputting the previous-output data 229 d, “t_(setup,FF)” may represent a setup time of the flip-flop 230 d, and “t_(sq,MUX)” may represent the delay of selectors 228 a-228 d from the time of receiving selecting data to outputting the respective output data 227 a-227 d.

In contrast, a conventionally implemented speculative DFE may have a timing requirement expressed by the following equation:

UI<t _(cq,FF) +t _(setup,FF) +t _(sq,MUX)

As illustrated by comparing the two equations, the timing constraint of the DFE circuit 200 (e.g., “4UI”) may be four-times that of the timing constraint of a conventionally configured DFE (e.g., “4UI”). The DFE circuit 200 may have a timing advantage over the conventionally configured DFE because the constant part of the two equations (e.g., t_(cq,FF)+t_(setup,FF)) may be a smaller percentage of the timing constraint even though some of the increased time associated with the timing constraint of the DFE circuit 200 is used by extra selectors. As such, the DFE circuit 200 of the present disclosure may be implemented in faster communication systems.

Modifications, additions, or omissions may be made to FIGS. 2A and 2B without departing from the scope of the present disclosure. For example, the clock rates may vary according to particular implementations. Additionally, which flip-flops sample data on the rising edge of an associated clock and which flip-flops sample data on the falling edge of an associated clock is given merely as an example implementation. Also, in some embodiments, the half-rate aligners and/or the quarter-rate aligners may be omitted. Further, the DFE circuit 200 of FIGS. 2A and 2B is described in the context of a single-tap DFE. However, a speculative DFE with more than one tap may be implemented in accordance to the present disclosure.

For example, FIGS. 3A and 3B illustrate an example embodiment of a two-tap speculative DFE circuit 300 (hereinafter “DFE circuit 300”) configured to operate at a quarter-clock rate, arranged in accordance with at least some embodiments of the present disclosure. The DFE circuit 300 may be substantially similar to the DFE circuit 200 of FIG. 2A, except, the DFE circuit 300 may perform ISI cancellation based on the first and second previous values of input data 301 received by the DFE circuit 300.

For example, a speculative analog circuit 302 of the DFE circuit 300 may include summing circuits 312 a-312 d and 314 a-314 d that may be configured to generate speculative data 311 a-311 d, and 313 a-313 d, respectively. The speculative data 311 a and 313 a may be associated with the summing circuits 312 a and 314 a adding an ISI cancellation value C₁ and an ISI cancellation value C₂ to the received input data 301. The ISI cancellation value C₁ may be associated with the ISI experienced by the input data 301 from the previous value of the input data 301. The ISI cancellation value C₂ may be associated with the ISI experienced by the input data 301 from the second previous value of the input data 301. The speculative data 311 b and 313 b may be associated with the summing circuits 312 b and 314 b adding the ISI cancellation value C₁ to the received input data 301 and subtracting the ISI cancellation value C₂ from the received input data 301. The speculative data 311 c and 313 c may be associated with the summing circuits 312 c and 314 c subtracting the ISI cancellation value C₁ from the received input data 301 and adding the ISI cancellation value C₂ to the received input data 301. The speculative data 311 d and 313 d may be associated with the summing circuits 312 d and 314 d subtracting both the ISI cancellation value C₁ and the ISI cancellation value C₂ from the received input data 301.

A half-rate sampling circuit 304 may be configured to sample the speculative data 311 a-311 d on the rising edge of a half-clock that has a clock rate that is half the clock rate associated with the input data 301 to generate even speculative data 315 a-315 d, similar to the half-rate sampling circuit 204 configured to generate the even speculative data 211 a and 211 b described with respect to FIGS. 2A and 2B. The half-rate sampling circuit 304 may be similarly configured to sample the speculative data 313 a-313 d on the falling edge of the half-clock to generate odd speculative data 317 a-317 d, similar to the half-sampling circuit 204 configured to generate the odd speculative data 217 a and 217 b described above with respect to FIGS. 2A and 2B.

The DFE circuit 300 may include a half-rate aligning circuit 306 configured to receive the even speculative data 315 a-315 d and odd speculative data 317 a-317 d. The half-rate aligning circuit 306 may be configured to substantially time align the even speculative data 315 a-315 d with the odd speculative data 317 a-317 d on the rising edge of the half-clock, similar to the half-rate aligning circuit 206 time aligning the even speculative data 215 a and 215 b with the odd speculative data 217 a and 217 b on the rising edge of the half-clock 205, described above with respect to FIGS. 2A and 2B.

The DFE circuit 300 may include a quarter-rate sampling circuit 308 configured to receive the even speculative data 315 a-315 d and odd speculative data 317 a-317 d. The quarter-rate sampling circuit 308 may be configured to generate even speculative data 319 a-319 d and odd speculative data 321 a-321 d based on a rising edge of a quarter-clock that has a clock rate that is one-fourth of the clock rate associated with the input data 301, similar to the quarter-sampling circuit 208 generating even speculative data 219 a and 219 b, and odd speculative data 221 a and 221 b described with respect to FIGS. 2A and 2B. The quarter-rate sampling circuit 308 may also be configured to generate next-even speculative data 323 a-323 d, and next-odd speculative data 325 a-325 d based on a falling edge of the quarter-clock, similar to the quarter-rate sampling circuit 208 generating the next-even speculative data 223 a and 223 b, and next-odd speculative data 225 a and described above with respect to FIGS. 2A and 2B.

A quarter-rate aligning circuit 310 of the DFE circuit 300 may be configured to receive the even speculative data 319 a-319 d, odd speculative data 321 a-321 d, next-even speculative data 323 a-323 d, and next-odd speculative data 325 a-325 d from the quarter-rate sampling circuit. The quarter-rate aligning circuit may be configured to substantially time align the even speculative data 319 a-319 d, odd speculative data 321 a-321 d, next-even speculative data 323 a-323 d, and next-odd speculative data 325 a-325 d on the rising edge of the quarter-clock, similar to the quarter-rate aligning circuit 210 time aligning the even speculative data 219 a and 219 b, the odd speculative data 221 a and 221 b, the next-even speculative data 223 a and 223 b, and the next-odd speculative data 225 a and 225 b, described above with respect to FIGS. 2A and 2B.

The DFE circuit 300 may include a digital filter 331 configured to generate output data 327 a-327 d and previous-output data 329 a-329 d, based on the output data associated with the two previous values of the input data 301, similar to the digital filter 231 generating output data 227 a-227 d and previous-output data 229 a-229 d based on the output data associated with the previous value of the input data 201, described above with respect to FIGS. 2A and 2B. For example, the digital filter 331 may include a selector 328 a configured to receive the even speculative data 319 a-319 d from the quarter-rate aligning circuit 310. The selector 328 a may also be configured to receive the previous-output data 329 d and 329 c that may be associated with two previous values of the input data 301 with respect to the value of the input data 301 associated with the speculative data 319 a-319 b. Based on the previous-output data 329 d and 329 c, the selector 328 a may select one of the even speculative data 319 a, 319 b, 319 c, or 319 d to generate the output data 327 a.

A selector 328 b may be similarly configured to select one of the odd speculative data 321 a, 321 b, 321 c, or 321 d to generate the output data 327 b based on the previous-output data 329 d and the output data 327 a. A selector 328 c may be similarly configured to select one of the next-even speculative data 323 a, 323 b, 323 c, or 323 d to generate the output data 327 c based on the output data 327 a and the output data 327 b. Further, a selector 328 d may be similarly configured to select one of the next-odd speculative data 325 a, 325 b, 325 c, or 325 d to generate the output data 327 d based on the output data 327 b and the output data 327 c.

Therefore, the digital filter 331 may be configured to generate output data 327 a-327 d associated with four consecutive values of the input data 301 in a parallel manner based on output values associated with the two previous values of the input data 301 with respect to the value of the input data 301 associated with the respective output value 327. Such a parallel configuration may relax the time constraints imposed on the digital filter 331 (and ultimately the speculative DFE circuit 300) because the output data 327 a-327 d may be sampled by the flip-flops 330 a-330 d at a clock rate that is one-fourth of the clock rate associated with the input data 301. Further, the addition of a tap may not change the critical path of the DFE circuit 300 with respect to the DFE circuit 200. Therefore, the additional tap may not change the timing constraint of the dual-tap speculative DFE circuit 300 with respect to the single-tap speculative DFE circuit 200.

Therefore, the dual-tap speculative DFE circuit 300, like the single-tap speculative DFE circuit 200 of FIGS. 2A and 2B, implemented based on a quarter-clock rate according to the present disclosure may have a timing advantage over a conventionally configured DFE. As such, the DFE circuit 300 of the present disclosure may be implemented in faster communication systems than some conventionally configured DFE circuits.

Modifications, additions, or omissions may be made to FIGS. 3A and 3B without departing from the scope of the present disclosure. For example, the clock rates may vary according to particular implementations. Additionally, which flip-flops sample data on the rising edge of an associated clock and which flip-flops sample data on the falling edge of an associated clock is given merely as an example implementation. Also, in some embodiments, the half-rate aligners and/or the quarter-rate aligners may be omitted. Further, the speculative DFE circuit 300 of FIGS. 3A and 3B is described in the context of a two-tap DFE. However, a speculative DFE with more than two taps may be implemented in accordance to the present disclosure.

FIG. 4 illustrates an example method 400 of relaxing a timing constraint associated with reducing inter-symbol interference (ISI) of input data. The method 400 may be performed by any suitable DFE circuit configured according to the present disclosure, such as the DFE circuit 200 described with respect to FIGS. 2A and 2B, and the DFE circuit 300 described with respect to FIGS. 3A and 3B. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation

Method 400 may start, and at block 402, an ISI cancellation value may be added to input data received by the DFE circuit at a first clock rate to generate first speculative data. In block 404, the ISI cancellation value may be subtracted from the input data to generate second speculative data. The first speculative data and the second speculative data may also be associated with the addition or subtraction of other ISI cancellation values with respect to the input data.

In block 406, the first speculative data and the second speculative data may be sampled at a quarter-clock rate that is one-fourth of the first clock rate. The sampling at the quarter-clock rate may be such that the first speculative data and the second speculative data may be associated with four consecutive values of the input data. Accordingly, as described above, a timing constraint associated with performing the ISI reduction may be relaxed.

In block 408, the first speculative data or the second speculative data may be selected as output data based on previous output data. The previous output data may be associated with any number of previous values of the input data depending on the number of taps of a DFE circuit. The first speculative data or the second speculative data may be selected within a time period associated with the timing constraint. Following the block 408, the method 400 may end.

The method 400 may be executed by a quarter-rate speculative DFE circuit configured according to the present disclosure to improve the timing constraints imposed on the DFE circuit. As such, the quarter-rate speculative DFE circuit may perform ISI reduction on input data that may be received at faster data rates than conventionally configured DFE circuits.

Modifications, additions, or omissions may be made to method 400 without departing from the scope of the present disclosure. For example, each block of the method 400 may include more or fewer operations than those described. Additionally, although the terms “first” and “second” are used to describe certain elements, these do not refer to the number of those elements, but are used to differentiate one from another. Further, other blocks and operations may be performed between each described block.

All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention. 

What is claimed is:
 1. A system for relaxing a timing constraint associated with reducing inter-symbol interference (ISI) of input data, the system comprising: a speculative analog circuit configured to: receive input data at a first clock rate; add an inter-symbol interference (ISI) cancellation value to the input data to generate first speculative data; and subtract the ISI cancellation value from the input data to generate second speculative data; and a sampling circuit communicatively coupled to the speculative analog circuit and configured to sample the first speculative data and the second speculative data at a second clock rate that is one-fourth of the first clock rate such that a timing constraint associated with performing the ISI reduction is relaxed.
 2. The system of claim 1, wherein the speculative analog circuit is further configured to: add a second ISI cancellation value to at least one of the first speculative data and the second speculative data; and subtract the second ISI cancellation value from at least one of the first speculative data and the second speculative data.
 3. The system of claim 1, wherein the timing constraint is relaxed by a factor of four.
 4. The system of claim 1, wherein four consecutive values of input data are associated with the first speculative data and the four consecutive values of input data are associated with the second speculative data.
 5. The system of claim 1, further comprising a digital filter communicatively coupled to the sampling circuit and configured to select the first speculative data or the second speculative data as output data based on previous output data, the digital filter configured to select the first speculative data or the second speculative data within a time period associated with the timing constraint.
 6. The system of claim 5, wherein the output data is associated with four consecutive values of the input data.
 7. The system of claim 5, wherein the previous output data is associated with one or more previous values of the input data.
 8. The system of claim 1, wherein the first speculative data and the second speculative data are based on one or more previous values of the input data.
 9. A method of increasing a timing constraint associated with reducing inter-symbol interference (ISI) of input data comprising: adding an inter-symbol interference (ISI) cancellation value to input data received at a first clock rate to generate first speculative data; subtracting the ISI cancellation value from the input data to generate second speculative data; sampling the first speculative data and the second speculative data at a second clock rate that is one-fourth of the first clock rate such that a timing constraint associated with performing the ISI reduction is relaxed.
 10. The method of claim 9, further comprising: adding a second ISI cancellation value to at least one of the first speculative data and the second speculative data; and subtracting the second ISI cancellation value from at least one of the first speculative data and the second speculative data.
 11. The method of claim 9, wherein the timing constraint is relaxed by a factor of four.
 12. The method of claim 9, wherein four consecutive values of input data are associated with the first speculative data and the four consecutive values of input data are associated with the second speculative data.
 13. The method of claim 9, further comprising selecting, within a time period associated with the timing constraint, the first speculative data or the second speculative data as output data based on previous output data.
 14. The method of claim 13, wherein the output data is associated with four consecutive values of the input data.
 15. The method of claim 13, wherein the previous output data is associated with one or more previous values of the input data.
 16. The method of claim 9, wherein the first speculative data and the second speculative data are based on one or more previous values of the input data.
 17. A decision feedback equalizer circuit (DFE) for relaxing a timing constraint associated with reducing inter-symbol interference (ISI) of input data comprising: a speculative analog circuit configured to: receive input data at a first clock rate; add an inter-symbol interference (ISI) cancellation value to the input data to generate first speculative data; and subtract the ISI cancellation value from the input data to generate second speculative data; a sampling circuit communicatively coupled to the speculative analog circuit and configured to sample the first speculative data and the second speculative data at a second clock rate that is one-fourth of the first clock rate such that a timing constraint associated with performing the ISI reduction is relaxed by a factor of four; and a digital filter communicatively coupled to the sampling circuit and configured to select the first speculative data or the second speculative data as output data based on previous output data, the digital filter configured to select the first speculative data or the second speculative data within a time period associated with the timing constraint.
 18. The DFE circuit of claim 17, wherein four consecutive values of input data are associated with the first speculative data and the four consecutive values of input data are associated with the second speculative data.
 19. The DFE circuit of claim 17, wherein the output data is associated with four consecutive values of the input data.
 20. The DFE circuit of claim 17, wherein the previous output data is associated with one or more previous values of the input data.
 21. The DFE circuit of claim 17, wherein the first speculative data and the second speculative data are based on one or more previous values of the input data. 